How is a chip actually made?

From sand to ingot to wafer

A leading-edge logic chip starts as silicon dioxide — ordinary silica sand — purified through a series of chemical reductions until it reaches what is called electronic-grade silicon, with impurity levels measured in parts per billion. The purified material is then melted in a quartz crucible at about 1414 °C, and a small single-crystal seed is dipped into the melt and slowly withdrawn while rotating. As the seed comes out, the molten silicon solidifies onto it in the same crystal orientation. The technique is called Czochralski growth, named for a Polish scientist who developed it in 1916 for an unrelated purpose. The result is a cylindrical single-crystal ingot, 200 or 300 millimeters in diameter, several meters long, weighing hundreds of kilograms.

The ingot is sliced with a diamond wire saw into circular wafers about 775 microns thick. Each wafer is polished to mirror flatness — the surface roughness is below half a nanometer, which is smaller than the silicon atomic spacing. A standard 300mm wafer costs roughly $100-200 in bulk for a polished blank, before any processing has been done to it. A leading-edge logic chip will have several hundred dollars added to that base cost in process steps before it is diced into individual die.

Almost all the world's wafer-grade silicon comes from a handful of suppliers: Shin-Etsu Chemical (Japan), SUMCO (Japan), Siltronic (Germany), GlobalWafers (Taiwan), and SK Siltron (Korea). These five companies control over 90% of the wafer-grade silicon market. The supply chain is a real bottleneck: when Shin-Etsu's Niigata plant flooded in 2022, the entire industry felt the supply pinch for nearly two quarters.

The thousand-step flow

Once a wafer enters the fab, it goes through what the industry simply calls "the line" — a sequence of typically 800 to 1,500 individual process steps, depending on the technology generation. Each step adds, removes, or transforms a thin layer of material on the surface of the wafer. The wafer travels through the fab in a sealed plastic container called a FOUP (Front-Opening Unified Pod) that holds 25 wafers and is moved between tools by overhead-track robots. A leading-edge wafer takes about three months to traverse the full line — wafer-start to die-out — which is one of the longest cycle times in modern manufacturing.

The steps cluster into a small number of repeated functional modules, run in different combinations for each layer of the chip:

• Deposition — adding a thin film of material. Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD). Films are typically a few atoms to a few nanometers thick. Applied Materials, Lam Research, ASM International, and Tokyo Electron dominate the deposition equipment market.
• Photolithography — patterning the layer with the chip design. Light through a mask projects the pattern onto a photoresist-coated wafer; the resist is then developed away in exposed (or unexposed) regions, leaving a stencil for the next step. ASML monopolizes EUV; ASML, Nikon, and Canon split the older DUV market. See the EUV deep dive for more.
• Etch — removing material from the unmasked regions. Plasma etch tools are the workhorse. Lam Research and Tokyo Electron together hold ~70% market share; Applied Materials is third.
• Ion implantation — driving dopant atoms (boron, phosphorus, arsenic) into the silicon at specific energies to create n-type or p-type regions. Applied Materials and Axcelis are the suppliers.
• Chemical Mechanical Planarization (CMP) — polishing the wafer flat between layers, so the next layer has a clean surface to build on. Applied Materials and Ebara are the leaders.
• Cleaning — between every step, the wafer is washed with high-purity chemicals to remove particles and residue. SCREEN, Tokyo Electron, and Lam are the suppliers.
• Metrology and inspection — measuring the wafer at intermediate steps to verify each step did what it was supposed to. KLA dominates this category with roughly 50% market share; Applied Materials and Hitachi are the alternates.

Where the leading-edge fab actually spends its money

A leading-edge fab — say, TSMC's N3 in Tainan — costs about $20 billion to build. Roughly 70% of that is equipment. The biggest single line item is lithography: a leading-edge fab needs 10-20 EUV scanners at roughly $180 million each (or $380 million each for the newer High-NA models), plus another 30-40 older DUV scanners. That is two to six billion dollars of one company's equipment in one fab.

Etch and deposition each account for another 15-20% of the equipment bill. Metrology runs 10-12%. The remaining equipment is split across thermal processing, implant, CMP, and cleans. The non-equipment portion of fab capex is buildings, cleanroom infrastructure (HEPA filtration that produces air with less than one particle per cubic foot at 100nm), water purification, exotic-gas handling, and waste treatment. A leading-edge fab uses roughly 4-10 million gallons of ultrapure water per day. Power draw is in the hundreds of megawatts.

The cleanroom is the part most lay readers underestimate. A single airborne particle of dust at 50nm landing on a wafer during processing can ruin the die. The cleanroom is maintained at ISO Class 1 to 3 — for context, a hospital operating room is ISO Class 7. Operators wear bunny suits with no exposed skin. The cleanroom HVAC system alone draws tens of megawatts. This is one of several reasons the trailing-node fabs cannot simply be retrofitted to run leading-edge processes: the cleanroom specs are tighter and the recirculation systems are more aggressive.

The equipment oligopolies

The structure to internalize is that almost every step of the fab process is controlled by a two-to-four-supplier oligopoly, and most of those suppliers are headquartered in the US, Japan, or the Netherlands. ASML (Netherlands) is the monopoly in EUV lithography. Applied Materials (US), Lam Research (US), and Tokyo Electron (Japan) together hold dominant share in deposition and etch. KLA (US) holds dominant share in metrology. ASM International (Netherlands) is the leading ALD supplier. There is no equivalent Chinese supplier in any leading-edge category, and the export controls (US BIS, Dutch export rules, Japanese restrictions) deny these tools to Chinese fabs at the most advanced nodes.

The implication is that even if China builds a domestic fab, it cannot operate at leading-edge nodes without the equipment, and the equipment cannot be built in China within an investment horizon anyone has been willing to commit to. The Chinese domestic equivalent companies — Naura, AMEC, ACM Research, SMEE — are competitive at trailing nodes (28nm and older) but several generations behind at leading edge. SMEE has reportedly demonstrated a domestic DUV scanner but is years from a production EUV equivalent. Whether the gap closes in five years or fifteen is the consequential question for the geopolitics of chip supply.

Strategic read

The chip-supply discussion in 2026 is dominated by fab capacity and lithography. The deeper truth is that fabs are downstream of a much smaller equipment supply chain, and the equipment supply chain is downstream of an even smaller set of materials suppliers (Shin-Etsu and SUMCO for wafers, JSR and Tokyo Ohka Kogyo for photoresists, Linde and Air Liquide for process gases, Zeiss for EUV optics). Each step is more concentrated than the one downstream of it.

For an operator-strategist, this means the leverage points in chip supply are at the materials and equipment layer, not at the fab layer. If you want to understand what gates Taiwan's ability to ship chips, ask about Zeiss' EUV optics production schedule rather than TSMC's fab utilization. If you want to understand what gates a Chinese leading-edge fab from existing, ask about SMEE and Naura rather than SMIC. The fab is the visible part of the iceberg; what is underneath is the supplier ecosystem that almost nobody outside the industry pays attention to and that almost completely determines whether the buildout happens or does not.