How the industry pushed transistors smaller for 30 years

The wavelength ladder

Optical lithography started in the 1980s with i-line lithography at 365 nm, generated by mercury vapor lamps. Then krypton fluoride (KrF) excimer lasers brought it down to 248 nm in the late 1990s. Then argon fluoride (ArF) excimer lasers reached 193 nm in the early 2000s. Each jump made finer features possible, and each took roughly a decade of cross-industry R&D to ship at volume.

Then ArF stalled. The industry could not find a shorter-wavelength excimer laser that worked at production volume, and waited two decades for EUV at 13.5 nm.

Source: Chris Miller, "Chip War"; ASML technical history

Immersion lithography: pour water on the wafer

When 193 nm ArF ran out of room, the industry shipped a hack that sounds absurd until you remember it works: pour ultra-pure water over the wafer between the lens and the resist. Water has a higher refractive index than air, which effectively shrinks the wavelength as the light hits the surface. Immersion lithography squeezed several more nodes out of 193 nm light and remained the workhorse of the optical era through the 45 nm node and below.

The whole optical era runs on the Rayleigh criterion: smallest printable feature scales with wavelength divided by numerical aperture. Immersion did not change the laser; it changed the medium between the laser and the wafer, which changed the effective wavelength.

Multi-patterning bought time, at 2× the cost per pass

When immersion ran out of room, the industry started exposing the same layer twice: first at the native pitch the tool could resolve, then shifted by a fraction of it. This is called LELE (litho-etch-litho-etch). For the smallest features the industry pushed to triple- and quad-patterning. The result was finer patterns from the same tool. The cost was that every extra pass roughly doubles the time on that step, doubles the defect risk, and pushes alignment tolerances tighter.

EUV's 13.5 nm light collapses many of those passes back into a single exposure. Every leading-edge logic node from TSMC N5 onward, plus the leading-edge DRAM that feeds HBM stacks, depends on EUV. There is no "we will do it with the old machines instead" for the chips that train and serve frontier AI.

The SMIC case study: DUV without EUV access

China's SMIC, locked out of EUV by US and EU export controls, has reached 7 nm class transistors on 193 nm DUV with aggressive multi-patterning. The chips exist; they ship in Huawei phones. The cost is yield and throughput: per-wafer cost is materially higher, and the practical ceiling sits around the 5 nm class with each extra node compounding the multi-patterning tax.

SMIC is the proof case that DUV multi-patterning is not done, just expensive. It is also the proof case for why everyone else wanted EUV the moment ASML could ship it.

Source: TechInsights teardowns of SMIC-fabricated parts, 2024-2025

Why DUV stalled, and what came next

DUV had three exits: a shorter wavelength laser, bigger optics, or both. None of the laser chemistries below ArF panned out at production volume. Optics could only widen so far before mask economics broke. The path forward was a jump to an entirely different physical regime, and that took ASML, Zeiss, Cymer, and the US national labs roughly two decades to make work at scale.

DUV is not gone. Trailing-edge and mature nodes still run on it, and SMIC is using it to push as far as multi-patterning allows. But the leading edge, and every chip that trains or serves frontier AI, moved to EUV.