RISC vs CISC and the birth of codesign
A simpler instruction set, codesigned with the compiler, beat the best individually-optimised chips. The bet originated at Stanford and Berkeley in the 1980s. NVIDIA spent the 2010s extending the same idea across the entire stack.
CISC: the maximalist instruction set
Complex Instruction Set Computing was the dominant approach into the 1980s. The chip exposed hundreds of specialised instructions, each capable of a complex operation: load-then-add-then-store, string-copy, decimal arithmetic. The hope was that powerful instructions would mean fewer of them, smaller programs, and faster execution.
The catch was that compilers struggled to use the full instruction set efficiently. The most powerful CISC instructions were rarely emitted by compilers. The transistors that implemented them were paid for but unused.
RISC: the codesign bet
Reduced Instruction Set Computing said: expose a smaller, simpler instruction set that compilers can actually target well. Use the freed transistors for cache, pipeline depth, and parallel execution units. Trust the compiler to schedule the simple instructions efficiently.
John Hennessy at Stanford and David Patterson at Berkeley led the academic case in the early 1980s. The MIPS architecture (Stanford) and SPARC, ARM, and the IBM POWER lineage all carried the bet forward. RISC instruction sets now dominate everything from phones to data centres.
The deeper idea: codesign
RISC won not because simpler chips are inherently better, but because the chip and the compiler were designed together. The architecture exposed what the compiler could exploit, and the compiler delivered code the architecture could execute fast. Optimise them as two halves of one system, not as separate problems with a hand-off between them.
That is codesign. It is the mental model behind every successful computing platform since: ARM in mobile, Apple Silicon, NVIDIA's CUDA stack, the TPU's tight integration with JAX and the XLA compiler.
Why this matters for AI
NVIDIA extended codesign far beyond instruction sets. The same mental model applies across CPUs, GPUs, interconnects, switches, storage, compilers, schedulers, and model architectures. When all of those are designed against each other rather than in isolation, the system delivers compounding speedups that no individual optimisation can match.
Jensen Huang, in his Stanford CS153 lecture, traced this lineage explicitly back to Hennessy. The path from RISC to NVL72 rack-scale computers is one continuous bet on codesign.
Source: Jensen Huang, Stanford CS153 Frontier Systems lecture, April 30, 2026 (https://cs153.stanford.edu/)