Why "doubling every two years"?

The 1965 article

In April 1965, the trade magazine *Electronics* asked Gordon Moore, then director of R&D at Fairchild Semiconductor, to write a short piece about the future of integrated circuits. The result was four pages titled "Cramming More Components Onto Integrated Circuits." Moore plotted the maximum number of components on an economically-optimal IC for each year from 1959 to 1965, drew a straight line through five data points, and observed that the count had been doubling every year.

He then predicted the doubling would continue for at least ten more years. He was guessing. The data series was four years old. The mechanism — that smaller transistors got cheaper per unit, that smaller chip areas had higher yield, that both forces compounded — was real, but the rate of doubling was an empirical guess that happened to be approximately right.

The article became famous because the prediction held. Components per chip in 1975 were almost exactly where Moore had drawn the line a decade earlier. The pattern continued through the 1970s, 1980s, and 1990s. The press began calling it Moore's Law in the early 1970s. By the time Moore became CEO of Intel in 1975, the prediction he had made as a thirty-six-year-old R&D director had become the planning baseline for an entire industry.

Source: Gordon E. Moore, "Cramming More Components Onto Integrated Circuits," *Electronics*, vol 38, no. 8, April 19, 1965. The full original is publicly available on the Intel website.

The 1975 revision

By 1975, Moore had spent ten years actually running a chip company and had better data. At a conference in December that year, he revised his own prediction: the doubling would continue, but at a two-year cadence rather than one-year, because the easy gains from shrinking each generation had been collected and remaining gains required harder engineering for each step. The two-year cadence held for another three decades.

In the intervening 35 years, the number of transistors on a leading-edge logic chip rose from about 4,000 in 1975 to over 5 billion in 2010. That is a factor of about 1.25 million. Achieving the same factor of improvement in, say, automobile fuel efficiency would mean a 2026 car gets several million miles to the gallon. The relentlessness of the trend deformed the surrounding economy: every industry that touched computing — telecommunications, finance, retail, media, eventually transportation and biology — was reshaped by the assumption that the substrate underneath would keep getting cheaper by orders of magnitude per decade.

What actually died — Dennard scaling, 2005

Moore's Law was always a count, not a property. The reason it mattered to the rest of the world was a sibling phenomenon called Dennard scaling, named for an IBM engineer who published the rules in 1974. Dennard scaling said: each time you shrink a transistor by some linear factor, the voltage and current it operates at scale by the same factor, so power density stays constant. That meant you could double transistor count every two years and keep clock frequency rising and not melt the chip.

For thirty years this held. CPUs went from 1 MHz in the early 1980s to over 3 GHz by 2004 without the dies catching fire. Then it stopped. Around the 90nm and 65nm process nodes, leakage current — electrons tunneling through transistor gates that should have been off — began contributing meaningfully to power dissipation. Voltage stopped scaling down. Power density started rising rather than holding constant. The Pentium 4 hit a thermal wall around 3.8 GHz in 2004, and the industry abandoned frequency scaling almost overnight.

The 2005 inflection is the most important and least-discussed event in modern computing. Before it, software performance improved by waiting. After it, software performance had to be extracted from parallel hardware — multiple cores, then many cores, then specialized accelerators for the specific workloads (graphics, AI, networking, video codecs) that justified their own silicon. The reason your laptop has eight CPU cores plus a GPU plus a neural-engine block plus a media engine, rather than one screamingly-fast core, is that Dennard scaling died twenty years ago and nobody has yet figured out how to bring it back.

The unbundling

After 2005, the various sub-trends that had moved together under the Moore's Law banner began visibly decoupling. Transistor count kept doubling, but on a slower cadence — closer to every three years than every two. Single-thread performance grew roughly 5% per year, down from 50%. Cost per transistor stopped falling in 2014; some analysts argue it started rising. Frequency stayed essentially flat. Power efficiency improved on its own schedule, mostly through better packaging and lower voltage operation. The industry replaced one neat line with five separate curves, each scaling at its own rate.

The practical consequence is that the question 'is Moore's Law dead' has no clean answer. If you mean transistors per chip, no — the count is still rising, and Blackwell at 208 billion transistors is forty times an H100 from three years earlier (admittedly via more aggressive packaging, but the count is real). If you mean cost per transistor, yes — and the consequence is that buying twice the compute now costs about twice the money, which it did not in 1995. If you mean frequency, frequency has been dead since 2005. If you mean power-efficiency improvement, it is still happening but slowly. Anyone who answers the question without specifying which sub-trend they mean is selling something.

The fab capex spiral and what "node" means now

In 1980, a leading-edge fab cost about $200 million. In 2000, it was about $2 billion. The 2026 estimate for a TSMC N2 fab is in the $25-30 billion range, and the High-NA EUV scanners required for N2 and beyond start at around $380 million each. The capex curve has been steeper than the price-of-the-chips curve, which means the economics of building leading-edge fabs only work for an oligopoly with massive volume amortization. There are exactly two leading-edge logic foundries left — TSMC and Samsung — with Intel attempting a return via its IDM 2.0 strategy. That number used to be twenty.

The other thing worth knowing is that "process node" names are now marketing labels, not physical measurements. Through the 1990s, the node number was roughly the smallest feature size on the chip — 250nm, 180nm, 130nm. Around the 22nm transition that connection broke. Today's "3nm" or "2nm" labels refer to nothing physical; the actual smallest features are 10-20× larger than the name suggests. Different foundries use different naming conventions for what is roughly the same generation of process. TSMC N3 and Samsung 3GAE are not built to the same dimensions; they are roughly comparable in transistor density.

For an investor or operator, the consequence is that node-name comparisons across foundries are nearly meaningless. The useful metric is logic transistor density (millions of transistors per square millimeter), which is reported in industry-standard ways. By that metric, TSMC has been ahead of Samsung by roughly one full generation since 2018 and ahead of Intel by 2-3 years until very recently.

Strategic read

Moore's Law in its original form is over, in the sense that the bundled exponential is over. The components that remain are valuable enough — transistor count still doubles every three years on the leading edge, energy efficiency still improves, packaging still tightens — that the industry continues to deliver more performance for the dollar to anyone willing to pay for the leading edge. But the price of leading-edge is rising, and the customer base willing to pay it has compressed to a handful of firms: NVIDIA, AMD, Apple, the hyperscalers, and the few crypto-mining and high-end consumer-chip companies that still ride at the front.

The AI infrastructure consequence is that node access is now a strategic asset, not a commodity. The reason Apple gets first allocation on TSMC N3 and N2, with NVIDIA second, has to do with prepayment commitments and volume guarantees that smaller buyers cannot match. The reason China cannot build a 5nm domestic fab is not because the physics is unknown — the physics is published; the equipment is known — but because the equipment supply chain (ASML, Applied Materials, KLA, Tokyo Electron, Zeiss) is denied export and cannot be assembled domestically inside a decade. Moore's Law as a planning tool has been replaced by Moore's Law as a geopolitical pressure point.

If you are tracking the AI buildout, the moves that matter are not whether transistors per chip keep doubling — they will, slowly — but whether the foundry that hosts the doubling stays competitive (TSMC), whether Intel's foundry pivot delivers (uncertain), whether China can build a parallel leading-edge stack (very unlikely before 2030), and whether the High-NA EUV ramp at ASML stays on schedule (it is, narrowly). These four questions matter more for the next five years of compute supply than any single Moore's-Law forecast does.