What's actually inside a 5 GW data center?
Most of the power lights up GPUs. The rest cools them, networks them, and survives the round-trip from the substation. The numbers below are where the watts actually go.
The watt budget, end to end
A modern AI data center is mostly a building wrapped around chips, with everything else in service of keeping those chips running. For every 100 watts coming in from the substation, roughly:
- ~60–70 W goes to the chips themselves — GPUs, CPUs, and HBM.
- ~15–25 W goes to cooling — chillers, pumps, CDUs, immersion loops.
- ~5 W goes to networking — switches, optics, NVLink/InfiniBand.
- ~5–10 W is lost to power conversion and distribution — UPS, transformers, PSU efficiency.
The single number that captures this is PUE — Power Usage Effectiveness, defined as total facility energy divided by IT energy. A PUE of 1.0 means every watt goes to compute. A PUE of 2.0 means half the watts heat the air outside. Best-in-class hyperscaler builds in 2026 hit 1.06–1.10. Legacy enterprise data centers still average 1.5.
The cooling problem nobody plans for
Chips dissipate almost all the energy they consume as heat. A B200 draws 1.2 kW; that's 1.2 kW of waste heat per chip, in a rack that holds 36 of them, in a row of racks that holds 8 racks. A single NVL72 rack pulls about 120 kW. A row of them, ~1 MW. A modest training cluster, ~50 MW of heat to move out of the building.
Air cooling stops working past about 50 kW per rack. Above that you need direct-to-chip liquid cooling — cold plates bolted to the GPU, with coolant pumped through them. Above ~150 kW per rack you need full immersion — the entire system submerged in dielectric fluid. Both are well-understood; both require plumbing the building, which means cooling becomes an architecture decision before the first server is racked.
The physical scale
A 1 GW data center is roughly:
- ~700,000 GPUs at ~1.4 kW each (mix of training and inference loads).
- Tens of millions of square feet across multiple buildings on a single campus.
- Dozens of MW-class transformers stepping 33 kV grid power down through 4 kV → 415 V → 48 V at the rack and finally ~1 V at the chip.
- Hundreds of kilometres of fiber and copper wired into a single fabric so that any GPU can talk to any other within a few microseconds.
A 5 GW campus is five of those, ideally co-located so they can share substations, cooling water, and a single low-latency fabric. The physical footprint approaches a square kilometre. Construction lead times are 3–5 years from first dirt to first GPU lit.
Power delivery, substation to silicon
The most underrated engineering inside the building is the round-trip from the grid to the chip. Power arrives at 33 kV from the utility — high enough that wires are thin and losses are tolerable. On site it gets stepped down through several stages: 33 kV → 4 kV (medium-voltage distribution inside the building), 4 kV → 415 V (the low-voltage feed to a rack), 415 V → 48 V (rack-level DC bus), 48 V → ~1 V (at the GPU's voltage regulator).
Each conversion loses 1–3% as heat. Compound that across five stages and you get the 5–10% distribution loss that shows up in the PUE budget. Newer architectures push 800 V DC at the rack to cut intermediate stages. Cumulative gains in this layer can shave 3–5 percentage points off facility-wide losses — not glamorous, but at 5 GW campus scale, equivalent to 150–250 MW of net compute capacity, recovered without buying more chips.
Why this matters for AI strategy
The “chip wars” framing of the last two years is correct but incomplete. Inside the building, the binding constraints rotate among silicon, cooling, and power delivery on roughly an 18-month cycle. A frontier-capable site in 2026 needs all three architectures aligned — direct-liquid or immersion cooling, 800 V DC distribution, and a substation built for full-rated draw on day one. Sites built for the 2023 standard cannot be retrofitted to 2026 spec without gutting them.
That is why hyperscalers are buying greenfield land and starting from a clean sheet rather than expanding existing campuses. And it is why the operators with the largest, most-modern contiguous footprints have a structural lead that is harder to compete away than the chip lead it sits on.